JEE Main 2025 Jan 29 Shift 1, Physics Q15: Logic Gates

JEE Main2025Jan 29, Shift 1Physics

For the circuit shown above, equivalent GATE is :

A
OR gate
B
NOT gate
C
AND gate
D
NAND gate

Solution

Construct the truth table for the circuit. With NAND of $A, B$ giving $\overline{A B}$ and NOR of $A, B$ giving $\overline{A + B}$ , the final NAND of these two is $\overline{\overline{A B} \cdot \overline{A + B}} = A B + (A + B) = A + B$ (using $A B \subseteq A + B$ ).

Tabulating directly:

A	B	Y
0	0	0
0	1	1
1	0	1
1	1	1

This is the OR-gate truth table.

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JEE Main 2025 Jan 29 Shift 1, Physics Q15: Logic Gates

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