Logic Gates

PhysicsElectronic DevicesFor JEE aspirants

Logic gates are digital circuits whose output, 0 or 1, follows a fixed logical rule of the inputs, written as a truth table or a Boolean expression. NOT, OR and AND are the basic gates; NAND and NOR are universal, because each alone can build every other gate. This page covers digital signals, gate symbols and truth tables, Boolean algebra and De Morgan's theorems, timing diagrams, universal gates, diode logic and ICs. Logic gates give quick, scoring questions in NEET and JEE Main.

On this page1Digital signals2Gates and truth tables3Boolean algebra4Waveforms5Universal gates6Identifying circuits7Diode logic and ICs8Revision

Key Formulas - Quick Reference

★ Must learn NOT: $Y = \overline{A}$ ; OR: $Y = A + B$ ; AND: $Y = A \cdot B$
★ Must learn NAND: $Y = \overline{A \cdot B}$ (0 only when all inputs are 1); NOR: $Y = \overline{A + B}$ (1 only when all inputs are 0)
XOR: $Y = A \oplus B = A \overline{B} + \overline{A} B$ (1 when the inputs differ); XNOR: $Y = \overline{A \oplus B}$ (1 when they are equal)
★ Must learn De Morgan: $\overline{A + B} = \overline{A} \cdot \overline{B}$ and $\overline{A \cdot B} = \overline{A} + \overline{B}$
Identities: $A + 0 = A$ , $A + 1 = 1$ , $A \cdot 0 = 0$ , $A \cdot 1 = A$ , $A + A = A \cdot A = A$ , $A + \overline{A} = 1$ , $A \cdot \overline{A} = 0$ , $\overline{\overline{A}} = A$
Absorption: $A + A B = A$ , $A (A + B) = A$ , $A + \overline{A} B = A + B$
★ Must learn Universal gates: NAND makes NOT ( $1$ gate), AND ( $2$ ), OR ( $3$ ); NOR makes NOT ( $1$ ), OR ( $2$ ), AND ( $3$ )
A gate with $n$ inputs has $2^{n}$ rows in its truth table
★ Must learn Output column for $A B = 00, 01, 10, 11$ : AND 0001, OR 0111, NAND 1110, NOR 1000, XOR 0110, XNOR 1001

1. Analog and Digital Signals

An analog signal is a voltage or current that varies continuously with time and can take any value in a range (the output of a microphone, a sine wave). A digital signal has only two allowed levels, written with the binary digits 0 and 1. In positive logic the high level, say $5 V$ , is 1 and the low level, $0 V$ , is 0.

Figure 1: An analog signal varies continuously; a digital signal has only two levels. In positive logic the high level (

5 V

here) is 1 and the low level (

0 V

) is 0.

A room light is a simple digital system: the switch is either ON or OFF (input) and the lamp is either lit, 1, or dark, 0 (output). Digital circuits built from logic gates run calculators, digital watches, computers, robots, industrial controls and telecommunication systems.

Why only two levels? A circuit only has to decide "high or low", so a noisy or slightly distorted signal (say $4.6 V$ instead of $5 V$ ) is still read correctly. This noise immunity is the main reason digital electronics replaced analog processing in computers and communication.

2. Logic Gates and Truth Tables

Logic gate: a digital circuit whose output is related to its inputs by a fixed logical rule. It is called a gate because it controls the flow of information.
Truth table: lists the output for every combination of inputs; $n$ inputs give $2^{n}$ rows.
Boolean expression: the same rule in algebra: $+$ means OR, $\cdot$ means AND and a bar means NOT.

Figure 2: The seven gate symbols. A bubble at the output means NOT, so NAND

= \overline{A \cdot B}

and NOR

= \overline{A + B}

. NOT, OR and AND are the basic gates; NAND and NOR are universal.

The five common gates are NOT, OR, AND, NAND and NOR; XOR and XNOR are built from them but are asked often enough to learn too. One table holds all of them:

$A$	$B$	NOT $\overline{A}$	OR	AND	NAND	NOR	XOR	XNOR
0	0	1	0	0	1	1	0	1
0	1	1	1	0	1	0	1	0
1	0	0	1	0	1	0	1	0
1	1	0	1	1	0	0	0	1

NOT (inverter): one input, one output; it gives the opposite of the input, $Y = \overline{A}$ .
OR: two or more inputs; $Y = 1$ if any input is 1, $Y = A + B$ .
AND: two or more inputs; $Y = 1$ only if all inputs are 1, $Y = A \cdot B$ .
NAND (NOT-AND): an AND followed by a NOT; $Y = 0$ only when all inputs are 1.
NOR (NOT-OR): an OR followed by a NOT; $Y = 1$ only when all inputs are 0, that is, neither one input nor the other is 1.
XOR (exclusive OR): $Y = 1$ when the inputs are different; XNOR gives 1 when they are equal (an equality detector).

Exam Trick

Remember only the odd row. AND is 1 only for 11; OR is 0 only for 00; NAND is 0 only for 11; NOR is 1 only for 00. A bubble flips the whole output column. The same rules hold for 3 or more inputs: a 3-input NAND is 0 only for 111, one row out of 8.

2.1 Switch analogy

Think of a closed switch as 1 and a lit lamp as 1. Switches in series behave as AND, switches in parallel as OR, and a switch connected across the lamp behaves as NOT.

Figure 3: A closed switch is 1 and a lit lamp is 1. With

A = 1

B = 0

: series (AND) gives

0

, parallel (OR) gives

1

, and a switch across the lamp (NOT) turns it off, so

Y = \overline{A} = 0

OR (inclusive)

Output 1 for $A B = 01, 10$ and $11$ . Column: 0111. Switches in parallel.

XOR (exclusive)

Output 1 for $01$ and $10$ only; 0 for 11. Column: 0110. $Y = A \overline{B} + \overline{A} B$ .

Quick Recall: tap to check

NAND gate with

A = 1

B = 1

: what is

Y

Y = \overline{1 \cdot 1} = 0

Which gate gives 1 only when both inputs are 0?

NOR.

How many rows does the truth table of a 3-input gate have?

2^{3} = 8

Key idea

AND needs all 1s, OR needs any 1, the bubble inverts. NAND is 0 only for all 1s; NOR is 1 only for all 0s.

3. Boolean Algebra and De Morgan's Theorems

Boolean algebra (after George Boole) works with variables that can only be 0 or 1. Its rules look like ordinary algebra with a few surprises: in Boolean algebra $1 + 1 = 1$ , because OR only asks whether any input is 1.

Law	OR form	AND form
Identity	$A + 0 = A$	$A \cdot 1 = A$
Null (dominance)	$A + 1 = 1$	$A \cdot 0 = 0$
Idempotent	$A + A = A$	$A \cdot A = A$
Complement	$A + \overline{A} = 1$	$A \cdot \overline{A} = 0$
Double NOT	$\overline{\overline{A}} = A$	$\overline{\overline{A}} = A$
Commutative	$A + B = B + A$	$A \cdot B = B \cdot A$
Distributive	$A (B + C) = A B + A C$	$A + B C = (A + B) (A + C)$
Absorption	$A + A B = A$	$A (A + B) = A$

De Morgan's theorems let you move a bar across an operator: break the bar and change the sign.

\overline{A + B} = \overline{A} \cdot \overline{B} \overline{A \cdot B} = \overline{A} + \overline{B}

The first says a NOR gate is an AND gate with inverted inputs; the second says a NAND gate is an OR gate with inverted inputs. Proof of the first by truth table (the last two columns match):

$A$	$B$	$A + B$	$\overline{A + B}$	$\overline{A}$	$\overline{B}$	$\overline{A} \cdot \overline{B}$
0	0	0	1	1	1	1
0	1	1	0	1	0	0
1	0	1	0	0	1	0
1	1	1	0	0	0	0

Key idea

De Morgan: break the bar, change the sign.

\overline{A + B} = \overline{A} \cdot \overline{B}

and

\overline{A \cdot B} = \overline{A} + \overline{B}

4. Timing (Waveform) Diagrams

Gates also reshape pulse trains. When the inputs are given as waveforms, the output changes only at an instant where some input changes, so the method is always the same:

Draw a vertical line at every edge of every input and label the instants $t_{1}, t_{2}, \dots$
In each interval read $A$ and $B$ (high $= 1$ , low $= 0$ ).
Apply the gate's rule to get $Y$ for that interval.
Draw $Y$ as flat segments that change level only at the marked instants.

Figure 4: Same inputs, two gates. OR output is high wherever either input is high (

t_{1}

t_{4}

and after

t_{5}

); AND output is high only where both are high (

t_{2}

t_{3}

Figure 5: NAND output is AND upside down. Both inputs are 1 only before

t_{1}

and from

t_{4}

t_{5}

, so

Y = 0

there and

Y = 1

everywhere else (interval values

0, 1, 1, 1, 0, 1, 1

Exam Trick

OR = union, AND = overlap. Shade the high parts of both inputs: the OR output is high wherever any shading exists; the AND output only where the shadings overlap. NAND and NOR are these outputs turned upside down. If one input of a NAND is held at 1, the output is just the other input inverted.

Key idea

Waveforms: cut time at every input edge, apply the truth table interval by interval; the output can change only at an input edge.

5. Universal Gates: NAND and NOR

NOT, AND and OR together can realise any logic function. A gate that can produce all three by itself is called universal: NAND and NOR are the two universal gates. That is why a chip maker can build a whole processor from one type of gate.

Figure 6: NAND alone makes every gate. Join the inputs: NOT (

1

gate). NAND then NOT: AND (

2

). Invert both inputs, then NAND:

\overline{\overline{A} \cdot \overline{B}} = A + B

, OR (

3

Figure 7: NOR alone also makes every gate. Join the inputs: NOT (

1

gate). NOR then NOT: OR (

2

). Invert both inputs, then NOR:

\overline{\overline{A} + \overline{B}} = A \cdot B

, AND (

3

Gate to build	NAND gates needed	NOR gates needed
NOT	1	1
AND	2	3
OR	3	2
NAND	1	4
NOR	4	1
XOR	4	5
XNOR	5	4

Exam Trick

1-2-3, and the names swap. With NAND: NOT 1, AND 2, OR 3. With NOR: NOT 1, OR 2, AND 3. The "own" function (AND for NAND, OR for NOR) needs only 2 gates: the gate plus one more as NOT.

JEE Advanced

XOR from four NAND gates. Let $P = \overline{A B}$ . Two more NANDs give $\overline{A P}$ and $\overline{B P}$ , and the fourth gives $Y$ $= \overline{\overline{A P} \cdot \overline{B P}}$ $= A P + B P$ $= P (A + B)$ $= \overline{A B} (A + B)$ . This is 1 only when exactly one input is 1, so $Y = A \oplus B$ with 4 gates (5 NOR gates are needed).

Half adder. Adding two bits gives Sum $= A \oplus B$ and Carry $= A \cdot B$ (for $1 + 1$ : Sum 0, Carry 1, the binary number 10). One XOR and one AND gate add two bits, which is how arithmetic starts in a processor.

Quick Recall: tap to check

Minimum number of NAND gates for an OR gate? For an AND gate?

3 and 2.

How is a NOR gate turned into a NOT gate?

Join its two inputs (or hold one input at 0).

Are XOR or AND gates universal?

No. Only NAND and NOR are universal gates.

6. Identifying Gate Combinations

Most exam questions give a small network of gates and ask which single gate it equals. Label every intermediate output, fill a 4-row truth table, then read the output column. The same few combinations come again and again:

Figure 8: Four combinations examiners love. (a) and (b) are NCERT Exercise 14.11. (c) and (d) are De Morgan's theorems:

\overline{A + B} = \overline{A} \cdot \overline{B}

and

\overline{A \cdot B} = \overline{A} + \overline{B}

Circuit	Output	Acts as
NOR, then NOT	$A + B$	OR
NAND, then NOT	$A \cdot B$	AND
NOT on each input, then NOR	$\overline{\overline{A} + \overline{B}} = A \cdot B$	AND
NOT on each input, then NAND	$\overline{\overline{A} \cdot \overline{B}} = A + B$	OR
NOT on each input, then AND	$\overline{A} \cdot \overline{B} = \overline{A + B}$	NOR
NOT on each input, then OR	$\overline{A} + \overline{B} = \overline{A \cdot B}$	NAND
NAND or NOR with inputs joined	$\overline{A}$	NOT
Two NOT gates in series	$A$	no change (buffer)

Bubble pushing. Moving a bubble from the output of a gate to all of its inputs (or the reverse) swaps AND with OR. So an OR gate with bubbles on both inputs is a NAND, and an AND gate with bubbles on both inputs is a NOR. Two bubbles on the same wire cancel.

XOR from basic gates. The expression $Y = A \overline{B} + \overline{A} B$ can be read straight off as a circuit: two NOT gates, two AND gates and one OR gate.

Figure 9:

Y

= A \cdot \overline{B} + \overline{A} \cdot B

= A \oplus B

uses 2 NOT, 2 AND and 1 OR gate. Output is 1 only when the inputs differ:

0, 1, 1, 0

for

A B = 00, 01, 10, 11

. (The hop shows wires crossing without a joint.)

Quick Recall: tap to check

NOT gates on both inputs of an AND gate give which gate?

NOR, since

\overline{A} \cdot \overline{B} = \overline{A + B}

A NOR gate followed by a NOT gate gives which gate?

OR (the two NOTs cancel).

Simplify

\overline{\overline{A}}

and

A + \overline{A} B

A

and

A + B

Key idea

Label, tabulate, compare: name every intermediate output, fill the 4-row table, and match the output column to a known gate.

7. Gates from Diodes, and Integrated Circuits

Gates are built from semiconductor devices. The simplest are made of diodes and a resistor (positive logic, $0 V = 0$ and $5 V = 1$ ). In the OR gate, any input at $5 V$ forward biases its diode and lifts the output; the other diode is then reverse biased and isolates its input. In the AND gate, any input at $0 V$ forward biases its diode and pulls the output down; the output stays high only when both inputs are high.

Figure 10: Diode-resistor logic (ideal diodes,

0 V = 0

5 V = 1

). OR: any high input forward biases its diode, so

Y = 1

. AND: any low input forward biases its diode and pulls

Y

0

; only

A = B = 1

leaves

Y

5 V

. With Si diodes the levels shift by

0.7 V

(OR high

4.3 V

, AND low

0.7 V

7.1 Integrated circuits (ICs)

An IC holds many transistors, diodes, resistors, capacitors and their connecting wires on one piece of semiconductor crystal (a chip), made by photolithography. Many logic gates are integrated in one chip.
The IC was invented by Jack Kilby at Texas Instruments in 1958; he received the Nobel Prize in Physics in 2000. ICs are found in cars, televisions, phones and almost every electrical device.
A microprocessor is an IC that processes all the information in a computer: keys pressed, programs, games.
Moore's law (Gordon Moore, co-founder of Intel): the number of transistors on a chip doubles at a steady rate, about every two years, while each transistor gets smaller and cheaper. Moore joked that if cars had improved as fast, a luxury car would travel half a million miles on a gallon and be cheaper to throw away than to park.

8. One-Mark Facts and Revision

Question	Answer
Basic gates	NOT, OR, AND
Universal gates	NAND, NOR
Gate with one input	NOT (inverter)
Rows for $n$ inputs	$2^{n}$
Bubble on a symbol	NOT (inversion)
Equality detector	XNOR
Positive logic	$1 =$ high ( $5 V$ ), $0 =$ low ( $0 V$ )
IC inventor	Jack Kilby, Texas Instruments, 1958 (Nobel 2000)

Use the flowchart for any gate or waveform problem, then the mind map for a last revision.

Figure 11: Problem-solving flowchart for gate questions. Memorise the output columns in the note: reading

Y

for

A B = 00, 01, 10, 11

names the gate in one glance.

Figure 12: Mind map for revision: every exam fact about logic gates on one screen.

9. Solved Examples

Solved Example 1

Inputs

A

and

B

of an OR gate vary as in Figure 4 (

A

high from

t_{1}

t_{3}

and from

t_{5}

t_{6}

;

B

high from

t_{2}

t_{4}

and after

t_{6}

). Find the output waveform.

Solution:

Interval	$A$	$B$	$Y$ (OR)
before $t_{1}$	0	0	0
$t_{1}$ to $t_{2}$	1	0	1
$t_{2}$ to $t_{3}$	1	1	1
$t_{3}$ to $t_{4}$	0	1	1
$t_{4}$ to $t_{5}$	0	0	0
$t_{5}$ to $t_{6}$	1	0	1
after $t_{6}$	0	1	1

Answer: $Y$ is low before $t_{1}$ and from $t_{4}$ to $t_{5}$ , and high in every other interval, as drawn in Figure 4. OR is 0 only where both inputs are 0.

Solved Example 2

The same inputs are applied to an AND gate. Sketch the output.

Solution:

Interval	$A$	$B$	$Y$ (AND)
before $t_{1}$	0	0	0
$t_{1}$ to $t_{2}$	1	0	0
$t_{2}$ to $t_{3}$	1	1	1
$t_{3}$ to $t_{4}$	0	1	0
$t_{4}$ to $t_{5}$	0	0	0
$t_{5}$ to $t_{6}$	1	0	0
after $t_{6}$	0	1	0

Answer: $Y$ is high only from $t_{2}$ to $t_{3}$ , the one interval where both inputs are high; it is low everywhere else (Figure 4).

Solved Example 3

A NAND gate has inputs:

A = 1

before

t_{1}

0

from

t_{1}

t_{3}

1

from

t_{3}

t_{5}

0

after

t_{5}

;

B

1

before

t_{1}

, then alternates

0, 1, 0, 1, 0

in the intervals up to

t_{6}

, and is

1

after

t_{6}

. Find

Y

Solution:

Interval	$A$	$B$	$Y$ (NAND)
before $t_{1}$	1	1	0
$t_{1}$ to $t_{2}$	0	0	1
$t_{2}$ to $t_{3}$	0	1	1
$t_{3}$ to $t_{4}$	1	0	1
$t_{4}$ to $t_{5}$	1	1	0
$t_{5}$ to $t_{6}$	0	0	1
after $t_{6}$	0	1	1

Answer: $Y = 0$ only before $t_{1}$ and from $t_{4}$ to $t_{5}$ , where $A = B = 1$ ; $Y = 1$ in the other five intervals (Figure 5).

Solved Example 4

Show that circuit (a) of Figure 8 (a NOR gate followed by a NOT gate) acts as an OR gate, and circuit (b) (NOT gates on both inputs of a NOR gate) acts as an AND gate.

Solution:

(a) The NOR output is $\overline{A + B}$ ; the NOT gate inverts it again:

$A$	$B$	$Y_{1} = \overline{A + B}$	$Y = \overline{Y_{1}}$
0	0	1	0
0	1	0	1
1	0	0	1
1	1	0	1

(b) The NOR gate receives $\overline{A}$ and $\overline{B}$ :

$A$	$B$	$\overline{A}$	$\overline{B}$	$Y = \overline{\overline{A} + \overline{B}}$
0	0	1	1	0
0	1	1	0	0
1	0	0	1	0
1	1	0	0	1

Answer: column $0111$ is OR, and column $0001$ is AND. By De Morgan, $\overline{\overline{A} + \overline{B}} = A \cdot B$ .

Solved Example 5

Identify the logic operation of two NAND circuits: (a) a NAND gate whose output feeds a second NAND gate with its inputs joined; (b)

A

and

B

each pass through a NAND gate with joined inputs, and the two outputs feed a third NAND gate.

Solution:

A NAND gate with joined inputs gives $\overline{A \cdot A} = \overline{A}$ , a NOT gate.

(a) $Y = \overline{\overline{A \cdot B}} = A \cdot B$ . Column $0001$ : AND.

$A$	$B$	$\overline{A}$	$\overline{B}$	$Y = \overline{\overline{A} \cdot \overline{B}}$
0	0	1	1	0
0	1	1	0	1
1	0	0	1	1
1	1	0	0	1

(b) Column $0111$ : OR (De Morgan: $\overline{\overline{A} \cdot \overline{B}} = A + B$ ).

Answer: (a) AND, 2 gates; (b) OR, 3 gates (Figure 6).

Solved Example 6

A

and

B

feed a NOR gate; its output goes to both inputs of a second NOR gate. Write the truth table and identify the operation.

Solution:

$A$	$B$	$Y_{1} = \overline{A + B}$	$Y = \overline{Y_{1} + Y_{1}}$
0	0	1	0
0	1	0	1
1	0	0	1
1	1	0	1

For $A = 0$ , $B = 1$ : $Y_{1} = 0$ , so both inputs of the second gate are 0 and $Y = 1$ . The other rows follow the same way.

Answer: OR (column $0111$ ): a NOR gate followed by a NOR used as NOT.

Solved Example 7

A gate gives

Y = 1, 0, 0, 0

for

A B = 00, 01, 10, 11

. The gate is
(A) AND
(B) NAND
(C) NOR
(D) XOR

Solution:

Answer: (C). The output is 1 only when both inputs are 0, the NOR rule $Y = \overline{A + B}$ . AND would read 0001, NAND 1110 and XOR 0110.

Solved Example 8

The Boolean expression

Y = \overline{\overline{A} + \overline{B}}

represents
(A) OR
(B) AND
(C) NAND
(D) NOR

Solution:

Answer: (B). By De Morgan, $\overline{\overline{A} + \overline{B}}$ $= \overline{\overline{A}} \cdot \overline{\overline{B}}$ $= A \cdot B$ , the AND function. Check one row: $A = B = 1$ gives $\overline{0 + 0} = 1$ , and every other row gives 0.

Solved Example 9

Simplify

Y = (A + B) (A + \overline{B})

Solution:

Distribute: $Y$ $= A \cdot A + A \overline{B} + A B + B \overline{B}$ $= A + A (\overline{B} + B) + 0$ $= A + A$ $= A$ .

Answer: $Y = A$ ; the output does not depend on $B$ at all. (Shortcut: the distributive law $A + B C = (A + B) (A + C)$ with $C = \overline{B}$ gives $A + B \overline{B} = A$ .)

Solved Example 10

Using the inputs of Figure 4, find the output of a NOR gate in each interval.

Solution:

Interval	$A$	$B$	$Y$ (NOR)
before $t_{1}$	0	0	1
$t_{1}$ to $t_{2}$	1	0	0
$t_{2}$ to $t_{3}$	1	1	0
$t_{3}$ to $t_{4}$	0	1	0
$t_{4}$ to $t_{5}$	0	0	1
$t_{5}$ to $t_{6}$	1	0	0
after $t_{6}$	0	1	0

Answer: the NOR output is the OR output of Figure 4 turned upside down: high only before $t_{1}$ and from $t_{4}$ to $t_{5}$ , where both inputs are 0.

Solved Example 11

In the diode OR gate of Figure 10,

R = 1 k Ω

A = 5 V

and

B = 0 V

. Find

Y

and the current in

R

for (a) ideal diodes, (b) silicon diodes with a

0.7 V

drop. Which diode conducts?

Solution:

$D_{1}$ has its anode at $5 V$ and conducts. $D_{2}$ then has its anode at $0 V$ and its cathode at the output (high), so it is reverse biased and carries no current.

(a) Ideal: $Y = 5 V$ and $I = \frac{5}{1000} = 5 mA$ .

(b) Silicon: $Y = 5 - 0.7 = 4.3 V$ and $I = 4.3 mA$ .

Answer: (a) $5 V$ , $5 mA$ ; (b) $4.3 V$ , $4.3 mA$ ; only $D_{1}$ conducts. $4.3 V$ is still read as logic 1.

Solved Example 12

The output of a NOR gate is 1. What are its inputs? What if the output of a NAND gate is 0?

Solution:

NOR is 1 only in the row $A = B = 0$ ; NAND is 0 only in the row $A = B = 1$ .

Answer: NOR output 1 means $A = B = 0$ ; NAND output 0 means $A = B = 1$ . Each gives one unique row, so the inputs are fixed completely.

Practice Questions

Write the truth table of a NAND gate whose two inputs are joined and fed by $A$ . Which operation does it perform?Answer: $A = 0$ : $Y = 1$ ; $A = 1$ : $Y = 0$ . It is a NOT gate.
A NOR gate has its inputs joined. A second circuit sends $A$ and $B$ through NOR gates with joined inputs and then into a third NOR gate. Identify both operations.Answer: First: NOT. Second: $\overline{\overline{A} + \overline{B}} = A \cdot B$ , AND.
Which gate gives an output 1 only when its two inputs are different?Answer: XOR
An AND gate is followed by a NOT gate. Find $Y$ for $A = 1$ , $B = 1$ and name the combination.Answer: 0; NAND
Simplify $Y = A + \overline{A} B$ .Answer: $Y = A + B$
A 3-input NAND gate: how many rows are in its truth table, and in how many is the output 0?Answer: 8 rows; output 0 only in one row ( $111$ )
What is the minimum number of NOR gates needed to make an AND gate?Answer: 3
In a NAND gate, $A$ is held at 1 and $B$ is a square wave $0, 1, 0, 1$ . What is the output?Answer: $1, 0, 1, 0$ : with $A = 1$ , $Y = \overline{B}$

Common Mistakes to Avoid

Watch out

Treating $+$ as ordinary addition. In Boolean algebra $1 + 1 = 1$ (OR), not 2.
Writing $\overline{A + B} = \overline{A} + \overline{B}$ . De Morgan: when the bar breaks, the sign changes, so $\overline{A + B} = \overline{A} \cdot \overline{B}$ .
Taking NAND as AND with inverted inputs. $\overline{A \cdot B} = \overline{A} + \overline{B}$ , while $\overline{A} \cdot \overline{B}$ is NOR.
Mixing up OR and XOR. They differ only for $A = B = 1$ : OR gives 1, XOR gives 0.
Missing an edge in a waveform problem. Mark every edge of every input; the output can change only there.
Using 2 NAND gates for OR or 2 NOR gates for AND. The own function needs 2 gates, the other needs 3 (NAND: AND 2, OR 3; NOR: OR 2, AND 3).
Calling AND, OR or XOR universal. Only NAND and NOR can build every other gate on their own.
Ignoring the $0.7 V$ drop in diode logic with silicon diodes: the OR high level is $4.3 V$ , and the AND low level is $0.7 V$ .

Frequently Asked Questions

What is a logic gate?

A logic gate is a digital circuit whose output, 0 or 1, follows a fixed logical rule of its inputs. Its behaviour is given by a symbol, a truth table listing the output for every input combination, and a Boolean expression. The common gates are NOT, OR, AND, NAND and NOR, with XOR and XNOR built from them.

Why are NAND and NOR called universal gates?

NOT, AND and OR together can realise any logic function, and a NAND gate alone can build all three: NOT with one gate, AND with two, OR with three. A NOR gate alone does the same: NOT with one, OR with two, AND with three. So a complete digital system can be made from only NAND or only NOR gates.

What is the difference between OR and XOR gates?

An OR gate gives 1 when at least one input is 1, including when both are 1. An XOR (exclusive OR) gate gives 1 only when the inputs are different, so for both inputs 1 it gives 0. Their output columns for inputs 00, 01, 10, 11 are 0111 and 0110.

What are De Morgan's theorems?

De Morgan's theorems say that the complement of A plus B equals A bar times B bar, and the complement of A times B equals A bar plus B bar. In words: break the bar and change the sign. They show that a NOR gate equals an AND gate with inverted inputs, and a NAND gate equals an OR gate with inverted inputs.

How do you find the output waveform of a logic gate?

Draw a vertical line at every instant where any input changes and label the instants. In each interval read the input levels as 0 or 1, apply the gate's truth table and draw the output as a flat level for that interval. The output can change only at an input edge, which makes the method quick and reliable.

How is an OR gate made from NAND gates?

Invert each input with a NAND gate whose two inputs are joined, then feed A bar and B bar into a third NAND gate. Its output is the complement of A bar times B bar, which by De Morgan's theorem equals A plus B. So three NAND gates make an OR gate, while two NAND gates make an AND gate.

Which logic gate questions come in NEET?

NEET usually asks for the output of a small combination of gates, the gate that matches a given truth table, NAND and NOR as universal gates, and output waveforms for given input pulses. Knowing the output columns of all gates and De Morgan's theorems lets you answer most of these in under a minute.

How are logic gates asked in JEE Main?

JEE Main gives a network of two to four gates and asks for its truth table or the single gate it equals, Boolean simplification with De Morgan's theorems, and timing diagrams. Circuits with NAND or NOR gates wired as inverters, and XOR built from basic gates, are common. Label each intermediate output to avoid errors.

Previous year questions on Logic Gates

21 questions from past papers, each with a step-by-step solution.

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